This invention is related to integrated circuit memories or any other type of integrated circuit having a data input and more particularly to a circuit and method for improving the data capturing accuracy of those integrated circuits.
In a typical integrated circuit memory, input data is captured using one or more differential input strobe circuits. Using the differential input strobes in true differential mode (i.e. both input to the same differential amplifier) results in an internal strobe signal that tracks the external strobes (provided by a system memory controller) well, but does not necessarily track the input data very well, which is of course the primary purpose of the data capture circuitry. This is especially true in regards to variation in data skew resulting from data ones being detected differently than data zeros by the primary differential input amplifiers. The input differential amplifier used by the strobes, since it has differential inputs, is mostly immune to these variations. The single-ended (data is compared against a fixed VREF voltage) data input amplifiers are subject to much more variations, which result in an undesirably reduced data capture window.
Referring now to FIG. 1, the prior art data capture method is shown. Both input data signals DQS and DQSB are inputs to differential amplifier 104. Both input data strobe signals DQS INPUT STROBE and DQSB INPUT STROBE are inputs to differential amplifier 102. Output signals DQS_CHIP and DQSB_CHIP are provided at the outputs of differential amplifiers 102 and 104. Since both data signals DQS and DQSB are inputs to differential amplifier 104, the internal DQS_CHIP signal switches based on the cross-over of the two inputs regardless of the relationship with the VREF (shown in FIG. 2). However, the data input pins (DINPAD) are referenced against a stable VREF (usually VCCQ/2) using differential amplifier 202. Therefore, internal skews from the din-pad switch point vary heavily on the VREF point and the characteristics of the differential amplifier as it relates to switching high and low about the VREF point. For skewed input conditions (e.g. strong logic ones, and weak logic zeroes). The data-in path does not track the strobe (DQS) input path very well since the strobe is based on a differential input scheme and is not subject to the same variations as is the single ended data-in path.
Referring now to FIG. 3, a timing diagram for a non-skewed “normal” prior art differential data capture method is shown. External data crosses VREF prior to DQS/DQSb crossing VREF (at the same time). This is referred to as the data set-up time (TDS). The internal delay of DATA_CHIP to DQS-CHIP should maintain this relationship right to the point where the DQS and DQSB strobes latch the data. This should be true for both data rising and falling and for both rising and falling edges of the DQS strobes (four cases total).
Referring now to FIG. 4, a timing diagram for a skewed prior art differential data capture method is shown. If the logic zeroes are uniformly “weak” for both strobes and data, the data is delayed by the full amount, but the DQS/DQSB crossover still determines the internal DQS trip point and these will be less than a “full” delay. Thus TDS and/or TDH (data hold time) problems will result.
What is desired, therefore, is a data capture system for an integrated circuit that will maintain uniform delays throughout the capture process so that the maximum window for capturing the data can be maintained and performance can be improved even in skewed conditions.